Re: Solid-state status

["Tesla list" <tesla-at-pupman-dot-com>]

Original poster: "by way of Terry Fritz <twftesla-at-uswest-dot-net>" <elgersmad-at-fnworld-dot-com>



You could also completely avoid cut off.  If you shut off a MOSFET
completely, it takes longer to turn back on but, if you allow it to
stay on per say the lowest output voltage being .7 volts, then the on
time is faster.  You will also need diode protection to prevent reverse
voltage transients from feeding back through the MOSFET.  It's pretty
simple, just allow for current flow in the direction that biasing
requires, and add zener diodes around the output to prevent
overvoltages across the drain and source.  The gate would be protected
by switching diodes, and zeners in parallel for the ideal surge
protection.  I no longer own a computer capable of graphics so, I
cannot explain very well.



-Vcc
|
|
-------|<--------     
|                |
|       \        |
|------->|-------|
|         \      |
|    R1          |
---\/\/\/\-------|
                |
                |----------to Gate
                |
|------>|--------|
|                |
|      \         |
|-------|<-------|
|        \       |
|    R2          |
---\/\/\/\-------|
|
|
Gnd



James.


-- Original Message As Follows --

Subject: Re: Solid-state status
From: "Tesla list" <tesla-at-pupman-dot-com>
To: tesla-at-pupman-dot-com
Date: Mon, 18 Dec 2000 11:29:00 -0700

Original poster: "R.E.Burnett by way of Terry Fritz
<twftesla-at-uswest-dot-net>" <R.E.Burnett-at-newcastle.ac.uk>


Hi Ken,

There are a couple of things that you can do to minimise the
"Miller" effect (caused by MOSFET Gate-Drain capacitance.)

1. Reduce the impedance of the gate drive circuit.  This involves 
minimising stray resistance and inductance in the entire gate-source
loop.
You could use a twisted pair if it is not practical to locate the
driver
stage close to the MOSFET gate terminals.  Keep PCB traces like 1/2" or
shorter in length,  and only add enough resistance to damp ringing.

2. Apply a small negative bias to the gate with respect to the source
of
the device that is intended to remain off.  If the gate is biased to 
10V
when off then the Miller effect must cause almost 13volts rise in the
gate potential in order to risk spurious turn-on.

( The negative gate bias method is a very effective "Miller killer" but
it
has one disadvantage.  Turn-on delay is increased because the gate now
has to be charged to the threshold voltage from -10volts or so ! )

I am not sure of your circuit topology (it is not published anywhere ?)
so I cannot really suggest any other tricks.  But,  I hope this info is
of
some help.
							Cheers,

							-Richie,




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