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Re: phase locked loop SSTC



Original poster: "Paul Nicholson by way of Terry Fritz <twftesla-at-qwest-dot-net>" <paul-at-abelian.demon.co.uk>

I wrote:
>> How far above Fres can you set the upper freq before problems
>> occur,  and what are those problems?

Jan Florian Wagner wrote:
> Can't set it above f_res more than 10-20kHz. The problem is with a
> high Q coil it looks like the PLL lands either on the lowest or
> highest freq in a "bad case", because there's no proper signal
> from the current sense.

You'll have to ensure that the feedback signal is present at a
sufficient level to lock, throughout the vco tuning range.  You 
only need phase, not amplitude, so a limiting amplifier before
the phase comparator might be called for.

> I actually have it working now, but there are some oddities:
> - the phase is not correct,

I expect you'll need to have a phase adjusting circuit, either in
the feedback chain, or between vco and comparator, or both.  Adjust
the phase for max base current.  Without this, the PLL will park the
frequency in the right ballpark, but you might easily be halfway down
(or more) the slope of the secondary response.  The PLL will try to
lock to a certain phase, and you need to fiddle the total loop phase
shift to make that 'certain phase' correspond to zero phase between
V and I at the coil base.

> Sometimes the PLL decides to lock to 90deg
> phase shift, and at other times 0deg. Arbitary.

Make sure the feedback circuit is not picking up a wiff of the
direct drive signal, ie your feedback signal should be sensitive to
coil base I not V.  Away from Fres, with V big and I small, your
feedback signal may be a mixture in which the I component no longer
dominates.  At best this will cause a phase error, at worst prevent
lock.  Capacitive coupling between windings of the current trans-
former could cause this.  If you use a CT on the sec base, put in
a shield winding, and make sure the feedback path is very well
screened.

> - with ground strikes the secondary jumps to the second harmonic!!
> very odd. 

Not strange at all.  Arc to ground from the topload makes a
fundamental change in the configuration of the resonator.  The
original resonance you were driving is converted to a high impedance
at a lower frequency, and the source is now presented with a low
impedance from the half-wave resonance.  

See
 http://www.abelian.demon.co.uk/tssp/tmp/pn1ld.unloaded.gif
 http://www.abelian.demon.co.uk/tssp/tmp/pn1ld.loaded.gif
for the impedance response of a coil, first with almost no load,
and the second with a heavy loading of just 1K top to ground.

Unloaded, we have 1/4 wave at 140kHz, 1/2 wave at 190 kHz.  Loaded,
the impedance response is inverted, and the 1/4 wave mode drops down
to 120kHz and the 1/2 wave mode rises to 340 kHz, not quite double
the original Fres.

With the top virtually shorted to ground, the half-wave resonance
now has the right change of phase with frequency for the PLL to
lock onto it.  Note that this is a *different* resonant mode to the
one being driven before the arc forms.  Hence a discontinuity must
occur in the drive signal as it jumps from the 1/4 wave mode to the
1/2 wave mode.  Whenever the load impedance at the top of the coil
falls below the transfer impedance of the secondary (ie the
characteristic impedance) the 1/4 wave resonance ceases to have the
right (-ve to +ve) phase change through resonance, instead it starts
to go +ve to -ve and the PLL is driven out of lock. If it then has
the locking range to find the 1/2 wave resonance and lock to it, you
would find yourself delivering power efficiently to the arc.

> The current is sinusoidal but two times the driver frequency.

Ok, that means your PLL is not making the jump.  Hence weedy
performance into the arc.  You've set an upper limit on the vco which
prevents the necessary tracking, in order to get stable operation
before arc.  I think you need to experiment to get a good wide,
reliable locking range - and then tell us all how to do it!!

> This strikes me as especially bad for a self-oscillating system
> with no frequency limit - locking on to 3rd harmonic isn't nice...

Indeed.  And making sure the driver can cope with all likely 
consequences of varying load conditions is a challenge that's
defeating me at the moment.  Note in the example above, the unloaded
3/4 wave at 355kHz is only just above the loaded 1/2 wave at 340 kHz.
Nasty!

> Output is not impressive at all, though... Maybe because
> 300-400kHz on PVC pipe is a bit lossy... ;o)

Maybe.  Have you measured the Q in order to estimate the top volts?
Do you get a better Q when driving the base from a padded signal
generator?  Can you get better output by tuning manually?

> I never understood this impedance matching business in conjunction
> with SSTCs 

Necessary to get the full power out of your driver.  Too low Zsec
and you reach limiting current before the variac gets to the top.
Too high Zsec and you reach the top of the variac before limiting
current.  Either way the VI product is less than your driver is
capable of delivering.  I think your web page already describes
this. 

> - I mean, driving at 50% duty always (i.e. NO current limiting via
> PWM) and always in-tune guarantees no power is reflected, so
> impedances are always matched.

I don't think it helps to think about forward and reflected power
and so on.  With a full bridge approximating a constant voltage
source, its output impedance should be effectively set by the current
limiting.  In practice I think the effective output impedance often
ends up being limited by the size of the reservoir caps on the DC
side of the driver.

Regards,
--
Paul Nicholson,
Manchester, UK
--