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Re: phase locked loop SSTC



Original poster: "Paul Nicholson by way of Terry Fritz <twftesla-at-qwest-dot-net>" <paul-at-abelian.demon.co.uk>

Jan,

The scope pictures helped a lot.  Ignoring all that high frequency
ringing, the waveforms look pretty good - roughly what I'd expect
to see.  You don't seem to be having any trouble at all from
higher overtones or harmonics of the drive signal.  Nor do you seem
to have any trouble with drive voltage coupling through the CT. 

I've annotated your low frequency picture in 

 http://www.abelian.demon.co.uk/tmp/jw-pll-preLock.gif

Notice that the current waveform is 90 deg ahead of the drive
voltage - that's spot on.

I've diagrammed the vco and current waveforms, as they would be
after being prepared for presenting to the comparator.

I've chosen to imagine a comparator whose output goes low on the
rising edges of the vco i/p, and goes high on the falling edges of 
the current signal.  Your comparator arrangement may be different to
this, but it's going to be equivalent.

You can see that,  with the vco well below Fres, current is 90 deg
ahead of voltage, and the comparator output has a 75% duty cycle.
If instead, the drive frequency was well above Fres, current would
lag by 90 deg and the comparator output would be 25% duty.

This means that, assuming a 5V rail for the comparator, its output
when smoothed will vary from 1.25V to 3.75V.  This must be amplified
quite a bit, and limited, to be useable as a vco control voltage.
I'm guessing that you may not have enough gain between the comparator
o/p and the vco tuning i/p. 

See also

 http://www.abelian.demon.co.uk/tmp/jw-pll-disLock.gif

for the case of vco above Fres. Now, current lags voltage - good.
Here, the comparator output is low, so this should be tuning the vco
down in frequency. It obviously isn't, or at least, not enough.

When locked, ie vco = Fres, comparator o/p should be very close to
50% duty,  and this should vary either side of 50% by only a very
few percent as the secondary Fres varies with load.  Thus the
smoothed output from the comparator should be around 2.5V +/- a
little. 

Let's put some numbers in to estimate the gain needed between 
comparator and vco control input:

At the half-power points of the coil's response, the current phase is
+/- 45 deg and the coil current is sqrt(2) of the maximum.   For
good performance, the pll must lock much closer to Fres than this,
say +/- 10 deg phase error max.  That means the comparator output
duty cycle will be between something like 48% to 52%.  Assuming a 5V
comparator, that's a smoothed output of 2.5V +/- 0.1V.

Now suppose your vco requires a tuning voltage of 0 to 10V to cover
the desired locking range. Then the comparator output would need
a level shift of -2.5V, followed by a gain of 100, followed by a 
level shift of +5V. 

Can you show us a circuit diagram of your phase comparator and vco -
perhaps you've already done that - forgive me if I've missed it.

Hope the above is not too confusing!  Summary:  The raw comparator
output duty varies 50% +/- 25% due to the impedance response of the
tuned load. This must be amplified so that the limited range, say 50%
+/- 2% expands to the full control voltage range of the vco.  Then
it will lock to Fres with at most 10 deg of residual phase error.

The HF ringing on the waveforms looks pretty bad, especially in
pll-disLock.  Any idea where it's coming from?  Maybe it's just an
artifact of the scope probing, but if it's coming from the driver,
it really needs to be identified and suppressed.

> About ignoring the 300Vpp primary square wave (half-bridge): is
> this really an issue?

Ah, I remember now, you're driving through a primary winding, so this
is probably not an issue.  Sorry, that's me being accustomed to
driving direct into the base, where it's a real problem.

> I can't get any real sinusoidal TC base current at much below
> (and above) Fres. Only close to Fres. Is it supposed to be like
> that?

Yup.  Expect a wriggly sawtooth. The zero crossings carry essential
information to the comparator.  Square it up if the comparator i/p
doesn't do that for you.

As you can see, tracking the wandering Fres of a tuned circuit is a
little different to the more normal usage of a PLL.  I'd like to hear
from anyone who's actually got this to work!

Cheers,
--
Paul Nicholson,
--