Fw: Fw: 10+MHz SSTC Gate Drive Circuit Finalized

["Tesla list" <tesla-at-pupman-dot-com>]

Original poster: "K. C. Herrick" <kchdlh-at-juno-dot-com> 


I've found a bit of time to tweak the design to eliminate the 1st-few-cycle 
problem.   I'll ask Terry to post it as

http://hot-streamer-dot-com/temp/ssdrvr-kch2.pdf

It's the charging of the 2 capacitors that's the problem: unbalanced 
current in each secondary.  To fix that I add capacitor/diode branches to 
balance the capacitor charging, plus resistors to ensure that the 
capacitors have = (i.e. 0) charge at the start.   Note that the waveforms 
show full symmetry after the 1st cycle.

My remaining concern is as to how the circuit will operate driving real 
MOSFETs & also whether there is sufficient non-overlap of the two 
anti-phase voltages.

Ken

kchdlh-at-juno-dot-com>
To: tesla-at-pupman-dot-com
Date: Thu, 18 Sep 2003 10:38:57 -0700
Subject: Fw: 10+MHz SSTC Gate Drive Circuit Finalized
MIME-Version: 1.0
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Full-Name: K. C. Herrick

Right!...I should have seen that.  I simulated that & it works...but I 
found that I had to reduce C2, C3 to 47nF; the 1 uF takes too long to 
charge.  Also, a) I don't think you need R1, R2 >ever< and b) you can omit 
CR1 & CR2 since the capacitors will charge nicely through the PNPs' b:c 
junctions, forward biased only when the PNPs stop being transistors 
anyway.  Seems odd to have a capacitor connected to a transistor collector 
with nothing else there, but in this case...why not?

With 47 nF for your C2/C3 & 5 nF loads, I get the load voltages reaching 8 
V in 40 us at 100 KHz.  >However<...I see a disturbing anomaly during that 
1st 40 us:  During the first several cycles after t=0 (when the C2/C3 
voltages rise from 0), both outputs become + at the same time!  That's 
something you might want to check (in the real world).  That's with the 
transformer being 2mH each coil, 1:1:1 and with k's = 0.9.  I'll pursue it 
further in simulation as soon as I can but probably not today due to the 
press of other things.

Ken Herrick

In a message dated 9/18/03 6:46:36 AM Pacific Daylight Time, 
tesla-at-pupman-dot-com writes:
Original poster: "Mccauley, Daniel H" <daniel.h.mccauley-at-lmco-dot-com>


Ken,

The mistake was that the P-Channel FET was just placed backwards on the
schematic. It will work fine
once you switch it around.  Also, though you really don't need a 10 ohm
resistor there, you need it
for any shoot-through conditions between the P-Channel FET and the NPN
transistor.

Dan



 > I tried simulating the circuit (in SIMetrix, -at- 100 KHz) & couldn't get
 > much out of it!  I thought to change it a bit & submit my
 > schematic, via
 > hot-streamer, at http://hot-streamer-dot-com/temp/ssdrvr-kch.pdf.
 >
 > A 20 V pp source drives the xfmr, simulating the "monster"
 > circuit.  In
 > the top secondary ckt, D1, C2 & Q1 are as before except C1's
 > capacitance
 > is much reduced (1 uF takes forever to charge; I'd be worried
 > about those
 > 1st few cycles as to MOSFET drive).  The MOSFET/10-ohm branch
 > is replaced
 > by Q2 and both Q1 & Q2 are driven via the D3/R1 pair.  D3
 > provides max.
 > drive for + excursions while R1 limits xfmr current during "-"
 > excursions.  (Without R1, Q2's b:c junction will short out TX1.)  R3
 > simulates TX1's resistance & R6 is for parasitic suppression
 > (in the real
 > ckt).  R2 damps oscillation a bit.
 >
 > Ken Herrick
 >
 >
 >