Re: 10+MHz SSTC Gate Drive Circuit Finalized

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Original poster: "K. C. Herrick" <kchdlh-at-juno-dot-com> 

I'll prevail on Terry to put up
http://hot-streamer-dot-com/temp/ssdrvr-kch5.pdf and
http://hot-streamer-dot-com/temp/ssdrvr-kch6.pdf.  These show the schematic
and simulation-waveforms of a s.s.-driver circuit that I think solves the
problem of drive-signal overlap.

TX1 drives 2 identical circuits that are shown grounded merely for
convenience of the simulation.  In the top one...

1.  Initial positive & negative excursions charge up C3 and C2, thus
keeping transformer loading symmetrical.  The  capacitors are charged
through the forward-biased b:c junctions of Q1 or Q2.  When not so acting
as charging-diodes, the transistors act as emitter followers to supply
the output signals.

2.  The circuit of D2, D1 and Q6 is what prevents signal overlap.  For
negative TX1 excursions, D1 conducts, bypassing D2 and Q6.  But for
positive excursions, the D2/Q6 branch remains non-conducting until TX1's
voltage becomes ~1.4 V more positive than the voltage on C3.  At that
point, Q6 turns on, pulling Q1's emitter to TX1's + voltage less ~1.4 V.

3.  By transformer action between the secondaries, at the instant Q6
starts to turn on, the Q3/Q4 output (in the lower circuit) must have
reached essentially 0 V.  The waveforms bear this out.  There is no
occasion when both outputs are positive at the same time except for the
very first transition after turn-on, when they are very briefly both
~+1.5 V.

4.  The unconventional connection of the return-sides of the output
signals establish the output baselines at 0 V.

5.  R3 ensures that the capacitors start out with 0 V (in the real
circuit); R3 & R5 may not be necessary.

6.  Pull-down resistors may be wanted should the drive circuits be
disconnectable from MOSFETs; the circuit works fine (in simulation, of
course!) with 4.7Ks.

This may very well solve my own problem; time will, I hope, tell.

Ken Herrick