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Re: SSTC, Modes and soft switching



Original poster: "Bob (R.A.) Jones" <a1accounting-at-bellsouth-dot-net> 

Hi all,

I had prepared responses to some issues but most have been already been
answered so I will just sum up  then add any questions I still have.

First if the input has a series C the input current must go to zero at some
point so soft switching is always possible.

Initially the softswitching frequency follows the transient current.  The
transient current  is the transient current for each mode so the drive
frequency will be approximately the geometric mean(as AQ puts it) of the
split frequencies.

As time progresses the transients decay but one decays faster than the other
so the softswitching frequency  shifts to maintain softswitching gradually
moving to the lower frequency mode which then exponential grows to a very
high value.  I assume all this is with out break out.

Unfortunately as the frequency is shifting any input power during the shift
may be wasted as it may not constructively sum at the output. However this
may be the price you have to pay for softswitching.

Yes there may be configurations that can peak in a few cycles but that
requires more peak current. The way to reduce the peak current is to operate
at a lower frequency and or use more cycles getting to the peak.

There appears to be a consensus growing that the primary must be tuned lower
than the secondary for best performance..

Steve:
Are you certain the current grows in the primary or secondary with out
limit. I would expect it to level off as the input power equals the losses
i.e. only finite Q or do the input power grow too?

How quickly does the frequency fall is that compatible with the Q's?  I
assume that was without break out. What happens with break out.

Third Harmonic:

The third harmonic of the drive has the opposite polarity at the peak of the
fundamental so 180deg phase shift is required if they are to add at the
output.  However that is the relationship between split modes.  Achieving
the coupling could be impractical.  Perhaps the 3/4 wave mode of the
secondary could be used but its difficult for me to see how it could be
arranged to be accurately three times the fundamental 1/4 wave mode given
that the 3/4 wave mode would be plus a little bit and 1/4 wave mode
truncated.

Bob





----- Original Message -----
From: "Tesla list" <tesla-at-pupman-dot-com>
To: <tesla-at-pupman-dot-com>
Sent: Tuesday, August 24, 2004 6:45 AM
Subject: RE: SSTC, Modes and soft switching


 > Original poster: "Steve Conner" <steve.conner-at-optosci-dot-com>
 >
 >  >Really, without load and with an output waveform that grows only to
 >  >a limit and then starts to fall, soft switching is not possible.
 >
 > I guess the corollary of this is, that if you force soft switching, the
 > output waveform must grow without limit :) I have observed this in
 > simulations and experiments. And it makes sense in theory too- if the
 > inverter voltage is held in phase with the primary current, then real
power
 > must be leaving the inverter at all times- the flow can't reverse.
 >
 > It really does happen, and is one of the things that makes DRSSTCs such
 > "fun" (the primary current grows without limit too)
 >
 >
 >  >The pll idea is conceptually elegant, but there is a problem:
 >  >How can the pll lock immediately, considering that the bursts are of
 >  >just a few cycles, and that the spacing between the zero crossings may
 >  >be not uniform? With any conventional pll, the first cycles would be
 >  >severely out of phase.
 >
 > In the (relatively loose coupled) coils I've played with so far, the rate
of
 > change of frequency is slow enough that the PLL can track it easily. The
 > rate of change of frequency seems to be a property of the coil system, not
 > the PLL.
 >
 > I set the PLL up so its unlocked frequency is equal to the resonant
 > frequency of the primary alone. So it is practically in lock to start
with.
 > I found experimentally that this setting gave the cleanest switching
 > overall. As the burst progresses I can see the frequency fall until it
 > reaches the lower split frequency. This is accompanied by a slight phase
 > error since the PLL needs an error signal to perform a frequency change.
 >
 > Because of the loose coupling and small tank capacitance I have been using
 > bursts of around 50 cycles to get enough bang energy. I'm going to try
 > tighter coupled coils next and will report on how it goes.
 >
 >
 >  >It's possible then
 >  >to have all the energy in the system at the output capacitance after a
 >  >single input cycle.
 >
 > The problem then is how to deliver a large amount of energy in such a
short
 > time- it leads to immense peak currents in the transistors. The DRSSTCs
 > built so far use 10 to 30 cycles and peak currents of 200 to 1500A.
 >
 >
 > Steve C.
 >
 >
 >