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Re: DRSSTC design procedure - draft
Original poster: "Bob (R.A.) Jones" <a1accounting-at-bellsouth-dot-net>
> Original poster: "Antonio Carlos M. de Queiroz" <acmdq-at-uol-dot-com.br>
implemented in my sstcd program.)
> 2) I know that the voltage gain is proportional to sqrt(Ca/Cb).
> (For mode x:x+2:x+4, x and odd integer, it is:
> Av=sqrt(Ca/Cb)*sqrt(x*(x+4))/2 )
> The maximum input current decreases if the inductances increase
> (probably a square root relation too, but I didn't verify).
> With all the design formulas implemented in my sstcd program (I still
> didn't write a page with the formulas...), I just have to adjust
> Ca until the voltage gain is high enough and then adjust Lb so
> the current is ok.
> In the example, I get the final element values:
> Ca= 105.0000000000 nF
> La= 28.9927583937 uH
> Cb= 50.0000000000 pF
> Lb= 60.0000000000 mH
> kab= 0.1205497549
> That results in:
> Output frequencies: 86478.14, 92057.37, 97636.61 Hz
> Voltage gain= 754.7350528497
> Bang energy (square wave input): 2.2185676457 J
> Maximum VCa (V)=-3242.78978 (0.55207 J) at 43.44887 us
> Maximum ILa (A)= 196.61827 (0.56041 J) at 46.05492 us
> Maximum VCb (V)=297670.20709 (2.21519 J) at 89.61579 us
> Maximum ILb (A)= 8.57035 (2.20353 J) at 92.31185 us
I notice that the output energy is approximately 4 x the max energy in the
primary C (Ca).
Is this generally true for the configuration/mode your suggesting?