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Re: Dan's ultrafast gate drive, schematic?
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- Subject: Re: Dan's ultrafast gate drive, schematic?
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- Date: Thu, 08 Sep 2005 16:43:59 -0600
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Original poster: Steve Conner <steve@xxxxxxxxxxxx>
Gah! I've only just got my PLL SSTC driver working, and it's obsolete
>It should be possible to get it to cope with variations in duty cycle,
>with a proper DC blocking capacitor, but it might be tricky
>to get it to work right.
Tricky is the word. The mean voltage across an inductor is always
zero. So if you're putting 3.3Vp-p through a gate drive transformer
with blocking capacitor, and the duty cycle is 90%, the positive
excursions will be 0.33V and the negative ones 2.97V. 0.33V isn't
really enough to turn on much of anything. I guess you could use a
blocking cap and clamp diodes for DC restoration, but then you'd have
to worry about the transient behaviour and the possibility of losing
the signal altogether during fast changes in duty cycle.
Ian de Vries's PhD thesis has some very interesting work on ultrafast
gate drives. His circuit can switch an IRFP460 in about 10ns. He uses
optocouplers and so can potentially handle any duty cycle. It would
make an excellent basis for a Class-D audio amp IMO. I couldn't find
his thesis for download any more, so I mirrored it on my own site: