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Re: Recent s.s.t.c. work



Original poster: "K. C. Herrick" <kchdlh@xxxxxxx>

Bevan (& all)-

This is excellent insight; continuing thanks!  Several responses:

1. Difficulty driving the IGBT capacitance is certainly a possibility. I'd think, tho, that I'd see an anomaly in the (differentially observed) gate waveform--and I did not, at least, in my quick look of the other day. I hope to take a closer look at that in the next few days. (Retired for years & getting on toward 80, I find my motivation is not what it was. And my smarts, for that matter...)

2. I am driving all 4 IGBTs of the H-bridge--with, of course, 4 identical drive circuits. As to overlap--yes, I've always tried to be careful of that (subsequent to the first time I found out about it the hard way)! In the present instance, Q1 (in TCH-DRVR) cannot turn on (by R3's current) until the input voltage passes 0 toward +. At the same time, due to tight magnetic coupling w/in the drive transformer, the drive to the other IGBT in the 1/2-H must necessarily (-?) be passing thru 0 toward -. Simulation shows overlap comfortably south of 0V.

Also, I have incorporated a low-ohm (100mV:50A) current shunt in the common connection of the + and - bridge-supply capacitors. I look at the voltage across that, differentially, while turning up the h.v. With proper phasing around the loop, I expect to see a wave looking like f.w.-rectified half-sines, at the Fr. With improper phasing, I will (and do, unhappily, so far) see parts of half-sines with abrupt transitions, indicative of non-zero-crossing switching. With crossover conduction, I should see spikes--and those, at least, I do not so far see.

3. As I'd mentioned in previous postings, I made an adjustable, digital, phase-shifter and incorporated it into the feedback loop. But then I had the short-circuit that zapped a brick, & I chose to re-do the driver circuits. At the same time I took out the phase-shifter, since additional simulation seemed to show that I could overcome the phase problem by going to a 1-turn feedback coil around the primary rather than the current transformer I'd previously used.

But it seems I still have an unacceptable phase shift resulting in non-zero-crossing switching--so I may have to reinstall the digital shifter.

4. I think I chose the CNY17-3 because it was relatively fast--but looking now at the data sheet, it doesn't look all that superior. I'd been using 4N35s. Can you suggest a better one?

5. Your point about the driver transformer is well taken; I've been worrying a bit about that. So your comment has prompted me, belatedly, to measure the inter-winding capacitance; I find about 160 pF. I have +/- ~150V supply rails so would experience a dV/dt of ~300V/200ns, or 1500V/us, seen by each of the "upper" windings of the H-bridge with respect to the supply--or 3000V/us with respect to each other. With I = CxdV/dt and dV/dt =3000V/us, the capacitive I would be ~1/2A if I have it right. Might be too much; hard to say. But no problem in the "low" windings, I'd think, since the capacitive currents from the high windings would tend to cancel. And there's also the same tight coupling to the primary, so with a low source-impedance, perhaps much of that current will end up passing thru the primary to the source. How does that sound?

I've wound the 3"-o.d. ferrite-toroid transformer bifilarly, using a length of multi-conductor, twisted, 20 ga. cable with the conductors then suitably interconnected to yield a 1:2:2:2:2 ratio, and ~1.5 mH primary inductance. So the magnetic and capacitive balance ought to be pretty good.

I have a 1/2-H simulated; perhaps I'll try adding some inter-winding capacitance & see what happens. So much less troublesome, sitting at the computer...

Ken Herrick


Tesla list wrote:
Original poster: "BNJ" <mailto:firebee@xxxxxxxxxxxxxxx><firebee@xxxxxxxxxxxxxxx>

Ken,
Ok on the transformer drive negative going input. That should work as you
have described and your transformer driver sounds a reasonable
configuration.

I'll volunteer another few speculative comments to consider.

First, it's possible that the driver doesn't like directly driving the
equivalent input capacitance at the IGBT gate and increasing R6 as you have
done, is effectively increasing the the driver output impedance to stabilise
its response. This is similar to the effect that happens with OpAmps when
they drive directly into too large a capacitive load.

Second, you haven't described whether you are actively driving more than one
IGBT (ie whether you are testing in half or full bridge configuration ?)
when you have the bridge supply active. Assuming you are driving at least a
half bridge, you should investigate whether you have any overlap (at the
driver outputs) between anti-phase pairs. If you study IGBT data sheets and
application notes you will observe that they generally turn off slower than
they turn on. That means that even with perfect antiphase drive signals, a
half bridge can have very substantial cross-conduction (shoot through)
current spikes (I've measured them!). If your drive signals are overlapping
at all due to unequal hi-low/low-hi propagation delays in the drivers, the
situation is even worse and the transients at the half bridge centre inject
unexpected energy back into the drivers. I have experienced driver output
device heating and failures at low bridge supply volts specifically from
this effect.

FYI - I have long run my brick bridges with adjustable dead-time
non-overlapping antiphase clocks. This eliminates any IGBT shoot through
completely and the drivers only need to contend with the Miller capacitance
charging/discharging effects. The down side of dead-time is that this adds
to the delay around the coil feedback loop and exacerbates non-zero crossing
switching of the IGBTs. I've cured all the loop delay issues as well by
including an adjustable phase advance system (not PLL) in the controller.
Zero crossing switching errors are then negligible.

Third: Another point to consider is the opto-coupler. The driver circuitry
is being taken for rapid 'rides' between the bridge supply rails. One
importance parameter for the opto's is the Common Mode Rejection slew rate.
When you get to 400V supply rails and IGBTs switching at around 200nsec, the
driver side of the opto is swinging at 8000V/usec with respect to the LED
input side of the opto. Capacitive coupling across the opto device can
result in erratic behaviour. The CYN17-3 data sheet I found didn't seem to
spec the CMR slew rate. I recommend you consider an opto with 10,000 to
15,000 V/usec CMR performance once you get any substantial supply volts on
the bridge. Optos with this CMR performance are available and usually have
internal electrostatic screens to shield the LED from the opto output
section. Another point with the CYN17-3 is that it is dead slow in terms of
propagation delay.

Fourth: The capacitance between windings of the input transformer needs to
be small, otherwise energy from the IGBTs is feeding back via the driver
output section components to charge/discharge the input transformer
interwinding capacitance.


Regards
Bevan J

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