Re: 10+MHz SSTC Gate Drive Circuit Finalized

["Tesla list" <tesla-at-pupman-dot-com>]

Original poster: "K. C. Herrick" <kchdlh-at-juno-dot-com> 

No one, including me heretofore, seems to have noticed that the NPN b:e
junctions are going to zener during negative excursions, in both the
(corrected) original circuit & in my alternates.  When each
output/source/emitter node stops going "-" at 0 V, the base/gate node
plunges merrily further "-".  Most NPNs will zener at 4-7 V & I've read
(perhaps an old-wives' tale) that such an event will ruin the
transistor's gain, for good.  The NPNs will draw that zener current thru
the 10 ohm resistors.

Gotta be a better way!

Ken Herrick