Re: 10+MHz SSTC Gate Drive Circuit Finalized

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Original poster: "K. C. Herrick" <kchdlh-at-juno-dot-com> 

Dan (& all)-

I'll prevail on Terry once again to post this revision--I hope, final--to
my suggested SSTC driver; http://hot-streamer-dot-com/temp/ssdrvr-kch7.pdf.
(He may also delete all the other ssdrvr-kch files to save himself some
HD space.)

In the simulation, I've followed Dan McCauley's suggestions in changing
R2 to 2 ohms & TX1's k to 0.99.  I also changed C4 & C7 to 40 nF and R1 &
R7 to 2 ohms.  Also found 220 nF better for C1, C2, C3, C5 & C6.  Also
added 470 ohms across each secondary; they were ringing a bit.

As before, in the top one of the 2 identical secondary circuits, C3
charges thru C2 and Q6 b:e while C2 charges thru D1 and Q2 b:c.  Emitter
follower Q2 is driven via D1 while e.f. Q1 is driven by Q6 via D2.  Q6
only turns on as a common-base-connected transistor when TX1's + output
exceeds C3's voltage by ~1.4 V; that's what prevents output-signal
overlap.

Because of the action of Q6, the output voltages never overlap at greater
than ~1 V except up to ~3 V during the first 3 half-cycles after turn-on.
  Rise & fall times between 10 and 4 V are a respectable 200 ns, & likely
better in real life with real & better transistors.

I've added b:e resistors here & there, also.

I realize that a plain-vanilla capacitor is a poor simulation of a
MOSFET; the MOSFET model I have with the (free) SIMetrix doesn't seem to
fully characterize the several non-linear capacitances so I don't bother
with it.

As I've said, I prefer this circuit (absent actual realization, of
course) to Dan's because a) the output signals don't overlap
(significantly) and b) no transistor zeners.

Ken Herrick