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[TCML] A s.s. "ring bridge"
I'd like to solicit opinions from the solid-staters on a scheme I've
been toying with. See http://drop.io/kch_ring_brg for schematics.
Ring-bridge.jpg shows the simulation drawing. It incorporates 6 power
transistors, MOSFETs or IGBTs, plus 6 capacitors, all connected into a
ring. (In the freebie-simulation, I have to use switches rather than
transistors.) Each capacitor is charged from the mains via an isolating
"common-mode" choke, and it is kept isolated from the others, for
charging from the mains, while the interposed transistors are off. Each
transistor is to be driven via an isolating transformer. Feedback to
start & maintain oscillation is taken from the return lead of the Tesla
coil's secondary and the primary is untuned.
The primary is connected to opposite sides of the ring. In the drawing,
it connects to the "emitters" of S2 and S6. Half the transistors (S2,
S3 and S5) are turned on during phase 1 of the drive and the others,
during phase 2. Because the capacitors are inductor-isolated from the
mains, each set of 3 becomes effectively connected in series during
alternate half waves of the drive signal. In that way, +/- (3x300V -
the various IR drops) becomes connected across the primary during each
The diodes D9, D10, D14, D11, D12 and D13 perform the function of
clamping each reverse-Vce transistor voltage to 600V peak, while at the
same time obviating an over-voltage problem should the transistors'
turn-off times differ.
In the simulation it works like a champ. In the hardware I would plan
to use ST STE40NK90ZD MOSFETs and CDE 942CDW2K capacitors--paralleled
with close-connected electrolytics--configured generally as shown in the
other drawing, RING-BRG.jpg. (Sorry about the low-res.)
RING-BRG.jpg shows what basic hardware configuration I have in mind.
Its main feature is a scheme for keeping stray inductance to a minimum
by the use of coaxial copper braid surrounding each tubular capacitor.
The charging chokes connect anywhere convenient, of course, but the
clamping diodes are to be connected closely to the ends of the
respective braids as shown: to a "+" at one end and a "-" at the other.
The capacitor leads are similarly connected. I don't show the
electrolytics, which would be connected as closely as possible to the
CDE capacitors. It's my feeling that by properly configuring the
braid-ends and the clamping diodes and by conforming the braids closely
to the o.d.s of the capacitors, I can effectively minimize the stray
inductances in the ring of diodes and capacitors. And, with this
configuration the MOSFET connections at the same time can easily be kept
very short. I would add varistors across the MOSFETS for additional
I show a simple transformer-isolated PNP/diode gate-drive scheme but I
suppose the rather high gate-capacitance of the ST MOSFETs might require
a more robust drive. I've developed a floating-supply drive with a
PNP/NPN pair that might do it.
The circuit has the advantage of safely allowing use of the 900V MOSFETs
while delivering perhaps +/-800V, and a hundred A or so during the
pulse-burst, into the primary--straight off-line from the 115V mains. I
plan to use MOSFETs rather than IGBTs because the Fr's of my two
secondary coils are 100 and 120 KHz--perhaps a little too high for
reliable IGBT switching, right?
This scheme is along the lines of the one s.s. coil I managed to get
going some years ago (see the photo at http://drop.io/pat_ck_dblH).
That was pretty satisfactory until it (was caused to) quit for good, and
I'd look for similar performance--with much less complexity--out of this
So...will anyone shoot it down? If it looks feasible I may or may not
give it a shot (maybe too old...rocking-chair beckons), but I would hope
someone else might have a go.
P.S. I'm to have a small "Gadget Freak" piece in Design News magazine
soon, about my T.c. work & with a pic of the 1-&-only coil. Don't know
if it's just on-line or also in the printed mag.
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