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Re: [TCML] understanding DRSSTC

   Hi Antonio,

I wrote a document with some simulations of a DRSSTC, designed with the method that I have developed:
The simulations show the compromises between operation at the central frequency, between the
two resonances, and operating at the resonances.
Operation at the resonances results in excessive primary current and inefficient switching, but you can vary
the output power up or down by changing the number of cycles in a burst.
Operation at the central frequency results, for a given output voltage, in the smallest possible input current, the fastest possible output voltage rise, and efficient switching. Operation with feedback from the primary current leads naturally to this mode of operation, at least with the system designed for this. The output power can be varied, but just down, with smaller number of cycles in a burst. More cycles than the designed maximum don't necessarily increase the output power in this mode. The design procedure assumes no load, as done in the design of a classical Tesla coil, but the consideration of a loaded system results in the same conclusions.

The central frequency can be made to match the secondary resonant frequency.
If you run at this frequency, the operating frequency will be equal to the secondary
frequency and this will give you the highest possible power transfer to the secondary.

The pole frequencies can never coincide with the secondary frequency due to the
coupling, so that running at their frequencies will require more primary current
to achieve a given power transfer.. I believe, this is what you observed.

But the central frequency has disadvantages: Consider a simple series tank.
If you drive it below the resonant frequency the current phase will lead the
input voltage. A PLL circuit would detect that and increase the frequency.
The central frequency has the opposite behaviour. There a drop in the frequency
leads to a current lagging the voltage. The PLL wouldn't lock on to it.
The pole frequencies on the other hand show the "normal" behaviour.

You could invert the feedback of the PLL, so that it locks onto the central
frequency, but I think, this is a fragile mode of operation, since the inverted
phase relation holds only between the poles. A glitch or a ground arc might throw
the PLL off.

Under heavy arc loading the central frequency will disappear. I believe
this to happen at about Qsec = 1/k In your simulation with k=0.12 that would be around Qsec = 8.
I've made measurements of arc load at 70kVpeak (at about 200kHz) and they give a
load resistance of about 100k. With the parameters you used, Qsec would drop to
about 2 with a 100k load.

My measurement was made under QCW conditions,
so that the arc had time to grow to its final size. With short burst, I'd expect the arc load
to be smaller. Nevertheless low Qsecs don't seem to be exotic. Under these conditions you'll
have only one ZCS frequency with a "normal" frequency-phase shift relation. An inverted
PLL will fail then.


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