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Re: [TCML] drsstc bus capacitors



| AFAIK the UD2.7 outputs are identical anyway. Are you suggesting there is an economic benefit to using each output to power separate GDTs with 2 secondaries as opposed to paralleling the outputs to power a single GDT with 4 secondaries?  I'm not intending to avoid 2 GDTs if there is any reason to have separate ones.
As to the bus caps, I don't suspect that they would have significantly higher ESL than other electrolytics. They all look to have about the same specs to me, but I've seen people warning others about non inverter grade electrolytics, but no real mention of the negative potential effects. If it's just an inductance thing that will show up as more ring at the inverter output, that can be checked at a low bus voltage as you suggest.  

Sent from Yahoo Mail on Android 
|  From:"Michael Barr-David" <michaelbd@xxxxxxxxxxxxxxx>
Date:Wed, Oct 14, 2015 at 3:38 PM
Subject:Re: [TCML] drsstc bus capacitors

 

Thomas

I suspect that you will just have to give the bus capacitors a go.  It isn't such a demanding application so they will probably work.  As I noted before, you do care about having a low impedance bridge power supply, but you can test that (at low voltage).

There are two points that I would add about having a lower tank inductance.  First, it will make tuning more fiddly in that the % change in inductance will be greater for the same tap change (one eighth turn etc).  Second, because DRSSTCs are usually current limited, max energy in the tank is linearly proportional to inductance.

UD2.7 sounds like a plan.  I have not thought about the pros and cons of paralleling the outputs in any depth, but I like the idea of having two separate circuits so comparisons can be made.  If the main advantage to paralleling is to avoid a second GDT, then I think that is a false 'economy'.

MBD

> On 15 Oct 2015, at 4:06 am, Thomas Shurtz via Tesla <tesla@xxxxxxxxxx> wrote:
> 
> 
>    ----- Forwarded Message -----
>  From: Thomas Shurtz <whompin105@xxxxxxxxx>
> To: Michael Barr-David <michaelbd@xxxxxxxxxxxxxxx> 
> Sent: Tuesday, October 13, 2015 1:47 PM
> Subject: Re: [TCML] drsstc bus capacitors
> 
> Thanks for the input.  I am still hoping someone will chime in on the bus caps.  I have been reading quite a bit here and on 4hv about acceptable primary impedance.  I've also spent a good amount of time playing with javatc.  A tank cap of 0.75 to 1.5 uF looks like it would be within the range of what other largish coils have had success with.  At 31 khz for a slightly detuned primary, a 1uF tank cap wants about 6 turns in a pancake coil.  That doesn't feel unreasonable, but my big SRSG coil had a much higher Fres and much smaller tank cap, so this is a bit outside my personal experience.  
> I do like the simplicity of a feedback based gate drive with over-current protection and undervoltage cutoff.  I'm thinking maybe a UD2.7 with the outputs paralleled on a single large GDT with 4 secondaries for all the bricks.
> Thomas
> 
> 
>    From: Michael Barr-David <michaelbd@xxxxxxxxxxxxxxx>
> To: Thomas Shurtz <whompin105@xxxxxxxxx>; Tesla Coil Mailing List <tesla@xxxxxxxxxx> 
> Sent: Thursday, October 8, 2015 3:28 PM
> Subject: Re: [TCML] drsstc bus capacitors
> 
> Thomas
> 
> I would not claim to be a DRSSTC expert but I've built one.
> 
> As to your question, the ESL of the bus caps is important.  As you point out below, one of the things that you want to do is have a low impedance design for the bus power supply.  In my case, either my implementation is poor (probably) or the electrolytics have a significant ESL (probably) but the result is I broke a few IGBTs by exceeding their max CE voltage before working out the problem and placing snubbers across the H bridge.  You have more headroom than I did (1600-680=920v) and so you might not have any problems.
> 
> As to your other comments, at a guess the tank cap sounds too big - it would force the primary inductance to be too low.  You should do some numbers and think about the need for there to be energy equivalence in the cap and coil in the primary tank circuit.
> 
> More generally, you would probably be well advised to spend some quality time with JAVATC.
> 
> When you say that you have not picked a gate drive design yet, how much pain do you plan to suffer?  The path of least resistance is probably going to be a UD2+ design.
> 
> MBD
> 
> 
> 
>> On 9 Oct 2015, at 6:31 am, Thomas Shurtz via Tesla <tesla@xxxxxxxxxx> wrote:
>> 
>> The design is not complete yet.  My budget is such that I'm designing to fit components as I obtain them rather than obtaining the components to fit a set design.  Currently I have:
>> - five CM600HA-24H IGBTs (good to have a spare right?) for a full bridge topology.- 1600V  200A  3phase bridge rectifier (planning to use just 1 of the 3 pairs of diodes though I might as well parallel them)- eight 3300V, 4500VDC peak, 6uF polypropylene GTO caps rated at 7200A peak current (should make for a pretty beefy tank cap between 0.75 and 3.0!! uF depending on how I series/parallel these).  That should allow me to go for either a high or low impedance design.- 20+ of the previously mentioned electrolytic capacitors (awaiting response from the list to see if I can try these before looking for something else)- two 1156 powerstat variacs (I expect I should be good for up to 15KVA or so -> maybe 10kW real power).
>> 
>> As of now the plan is to use the variacs to feed a voltage doubler for up to 680V at the bus.  I have designed what should be a minimal inductance bus for the bridge/lytic cap connections using aluminum angle extrusion.  I figure I'll wind a 48" to 60" secondary on 12" nominal PVC unless I come across a good deal on something else to use as a form.  I haven't yet determined what size wire.  A 10 lb spool of 24 AWG or 11 lb spool of 23 AWG should be good for 2000-2400 turns.  With a 12"x48" ish toroid that should keep my natural freq. low.  Shooting for around 30-35kHz loaded.  I still haven't thought through all the implications/differences of choosing to use a high capacitance MMC with low turn primary vs a smaller MMC (physically larger since it will use more of my caps in series) and long primary.  I will probably be seeking some advice here when the time comes.  I haven't picked a gate drive design yet, but I'm leaning toward a GTD approach.  
>> Thomas
>> 
>>      From: "msweeney23@xxxxxxxxx" <msweeney23@xxxxxxxxx>
>> To: Tesla Coil Mailing List <tesla@xxxxxxxxxx> 
>> Sent: Thursday, October 8, 2015 11:49 AM
>> Subject: Re: [TCML] drsstc bus capacitors
>> 
>> I cant say anything on the caps but would be interested in what design you are using, if its possible to share?
>> 
>> Regards,
>> 
>> Matt
>> 
>> ----- Reply message -----
>> From: "Thomas Shurtz via Tesla" <tesla@xxxxxxxxxx>
>> To: "Tesla Coil Mailing List" <tesla@xxxxxxxxxx>
>> Subject: [TCML] drsstc bus capacitors
>> Date: Thu, Oct 8, 2015 11:21 AM
>> 
>> I have a bunch of Hitachi electrolytic capacitors that came out of some old discarded industrial equipment (I believe it was a VFD for an elevator) They are HCGF3A series, and I can't find datasheets on them.  They are 450v 5600uF caps and I have a good 2 dozen of them.  I was thinking of using them for a CM600 based DRSSTC.  On the one hand I feel like the lytic specs aren't all that important, and the datasheets on the hgcf5a and f6a series caps (which might be the newer versions of what I've got?) look like they would be suitable for this use, but the screw terminals on my caps look kinda small (about 1 cm diameter) for the cap size (about 10cm diameter) which hints that they might not be the right thing for the job.  What do I stand to lose if I try these out and they aren't up to the right specs?  I mean they are free so I'm not out anything if I blow the juice out the vent hole on a few of them, but what other problems might I see?  What failures have people seen that 
>> they blame on poor bus/doubler electrolytics?
>> Thomas
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