Re: Is a PLL-synchronised SR SSTC possible?

["Tesla list" <tesla-at-pupman-dot-com>]

Original poster: "Jan Wagner by way of Terry Fritz <teslalist-at-qwest-dot-net>" <jwagner-at-cc.hut.fi>


On Tue, 25 Feb 2003, Tesla list wrote:
 > Original poster: "Jolyon Vater Cox by way of Terry Fritz 
<teslalist-at-qwest-dot-net>" <jolyon-at-vatercox.freeserve.co.uk>
 >  > Original poster: "Jan Wagner by way of Terry Fritz <teslalist-at-qwest-dot-net>"
 > <jwagner-at-cc.hut.fi>
 >  >
 >  > 2) for obvious reasons, you'd want to restrict the PLL tracking freq
 >  > range, so that the TC harmonics are well outside this range and you don't
 >  > t.ex. land too close to the "early start" of 3/4 f_res, so that the minor
 >  > phase shift caused there would try to drive the PLL up, towards 3/4 
f_res.
 >  > Then the PLL just hangs at its upper frequency bound forever...
 >  >
 > Aren' t the 3/4 wave, 5/4 wave, 7/4 wave and subsequent series resonant
 > modes weaker in amplitude to the 1/4 wave mode?

Yes

 > Therefore, by "de-sensitising" the transducer to signals of less than a
 > certain amplitude, might it not be possible to preclude oscillation at
 > frequencies other than the quarter-wave mode?

True...
Some (untried) options come to mind: 1) a steep low-pass filter
i.e. the filter phase change happens accross a small band only around the
-3dB. But, a steep filter is complex...

           |
           |     |
           |     |     | 3/4w loaded
           |     |     |
|----------------------------> freq
         1/4w    1/4w
         loaded  unloaded
   <----------------^ steep low-pass

(just a no scales sketch)

2) input hysteresis, minimum low<->high voltage levels, requires
experimentation for those adjustemts, and they depend on power levels.
The PLL center (or top) freq would have to be manually tuned to f_res, so
that after startup, the VCO freq wanders up towards f_res where the TC
finally can get a strong enough feedback signal to pass the input Schmitt
trigger and get the PLL into tracking mode

3) invent your own :-) Probably there's some easier way than the above
ones.

OTOH in my opinion and experience, the PLL SSTC is too complicated (vs
performance gain) and too unflexible to be of much practical use in solid
state coiling. Just my opinion.


A more comfortable design, similar to a PLL, might be:
feedback signal => fast ADC => DSP/FGPA core doing FFT (maybe even in
hardware, no extra programming)
=> detect FFT peak => output the frequency of that peak, maybe on timer or
PWM output pin => done

Should be a piece of cake with those modern high freq IF or RF sampling
chips for Digital Down Conversion, DDC. Mainly a matter of programming.
Sort of a "Software Steered TC". Got new SSTC firmware upgrades, anyone?
;-)

cheers,

  - jfw

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  Jan OH2GHR